DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 94

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

2–88
Figure 2–73. Arria GX IOE in DDR Input I/O Configuration
Notes to
(1) All input signals to the IOE can be inverted at the IOE.
(2) This signal connection is only allowed on dedicated DQ function pins.
(3) This signal is for dedicated DQS function pins only.
(4) The optional PCI clamp is only available on column I/O pins.
Figure 2–74. Input Timing Diagram in DDR Mode
Arria GX Device Handbook, Volume 1
Column, Row,
Figure
Interconnect
or Local
2–73:
ioe_clk[7..0]
Input To
Logic Array
DQS Local
Bus (2)
Data at
input pin
CLK
sclr/spreset
clkin
ce_in
aclr/apreset
Chip-Wide Reset
B0
A0
B1
A0
B0
A1
B2
A1
B1
Input Register
Input Register
CLRN/PRN
D
ENA
CLRN/PRN
D
ENA
Input RegisterDelay
A2
(Note 1)
I
nput Pin to
B3
A2
B2
Q
Q
A3
D
ENA
CLRN/PRN
B4
A3
B3
To DQS Logic
Latch
Block (3)
Q
VCCIO
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
VCCIO
PCI Clamp (4)
Bus-Hold
Termination
Circuit
On-Chip
Programmable
Pull-Up
Resistor
I/O Structure