DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 30
DK-DEV-1AGX60N
Manufacturer Part Number
DK-DEV-1AGX60N
Description
KIT DEV ARRIA GX 1AGX60N
Manufacturer
Altera
Series
Arria GXr
Type
FPGAr
Datasheet
1.EP1AGX20CF484C6N.pdf
(234 pages)
Specifications of DK-DEV-1AGX60N
Contents
Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
For Use With/related Products
1AGX60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2372
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2–24
Table 2–6. Reset Signal Map to Arria GX Blocks
Calibration Block
Transceiver Clocking
Arria GX Device Handbook, Volume 1
rx_digitalreset
rx_analogreset
tx_digitalreset
gxb_powerdown
gxb_enable
Reset Signal
Table 2–6
circuitry affected by each signal.
Arria GX devices use the calibration block to calibrate OCT for the PLLs, and their
associated output buffers, and the terminating resistors on the transceivers. The
calibration block counters the effects of process, voltage, and temperature (PVT). The
calibration block references a derived voltage across an external reference resistor to
calibrate the OCT resistors on Arria GX devices. You can power down the calibration
block. However, powering down the calibration block during operations can yield
transmit and receive data errors.
This section describes the clock distribution in an Arria GX transceiver channel and
the PLD clock resource utilization by the transceiver blocks.
Transceiver Channel Clock Distribution
Each transceiver block has one transmitter PLL and four receiver PLLs.
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lists the reset signals available in Arria GX devices and the transceiver
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© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
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