DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 20

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

2–14
Figure 2–14. Deserializer
Note to
(1) This is a 10-bit deserializer. The deserializer can also convert 8 bits of data.
Arria GX Device Handbook, Volume 1
Figure
2–14:
Word Aligner
The deserializer block creates 8- or 10-bit parallel data. The deserializer ignores
protocol symbol boundaries when converting this data. Therefore, the boundaries of
the transferred words are arbitrary. The word aligner aligns the incoming data based
on specific byte or word boundaries. The word alignment module is clocked by the
local receiver recovered clock during normal operation. All the data and programmed
patterns are defined as “big-endian” (most significant word followed by least
significant word). Most-significant-bit-first protocols should reverse the bit order of
word align patterns programmed.
This module detects word boundaries for 8B/10B-based protocols. This module is
also used to align to specific programmable patterns in PRBS7/23 test mode.
Pattern Detection
The programmable pattern detection logic can be programmed to align word
boundaries using a single 7- or 10-bit pattern. The pattern detector can either do an
exact match, or match the exact pattern and the complement of a given pattern. Once
the programmed pattern is found, the data stream is aligned to have the pattern on
the LSB portion of the data output bus.
XAUI, GIGE, PCI Express (PIPE), and Serial RapidIO standards have embedded state
machines for symbol boundary synchronization. These standards use K28.5 as their
10-bit programmed comma pattern. Each of these standards uses different algorithms
before signaling symbol boundary acquisition to the FPGA.
Pattern detection logic searches from the LSB to the MSB. If multiple patterns are
found within the search window, the pattern in the lower portion of the data stream
(corresponding to the pattern received earlier) is aligned and the rest of the matching
patterns are ignored.
Received Data
Recovery
(Note 1)
Clock
Unit
High-speed serial recovered clock
Low -speed parallel recovered clock
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
10
© December 2009 Altera Corporation
To Word
Aligner
Chapter 2: Arria GX Architecture
Transceivers