DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 79

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Table 2–18. Arria GX PLL Features (Part 2 of 2)
Figure 2–61. PLL Locations
© December 2009 Altera Corporation
Number of feedback clock inputs
Notes to
(1) For enhanced PLLs, m, n range from 1 to 256 and post-scale counters range from 1 to 512 with 50% duty cycle.
(2) For fast PLLs, m, and post-scale counters range from 1 to 32. The n counter ranges from 1 to 4.
(3) The smallest phase shift is determined by the voltage controlled oscillator (V
(4) For degree increments, Arria GX devices can shift all output frequencies in increments of at least 45. Smaller degree increments are possible
(5) Arria GX fast PLLs only support manual clock switchover.
(6) Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data channel to generate
(7) If the feedback input is used, you lose one (or two, if f
(8) Every Arria GX device has at least two enhanced PLLs with one single-ended or differential external feedback input per PLL.
depending on the frequency and divide parameters.
txclkout.
Table
2–18:
Feature
PLLs
FPLL7CLK
FPLL8CLK
CLK[3..0]
Figure 2–61
Figure 2–62
outputs and side clock pins. The connections to the global and regional clocks from
the fast PLL outputs, internal drivers, and CLK pins on the left side of the device are
shown in
7
1
2
8
Table
shows a top-level diagram of the Arria GX device and PLL floorplan.
and
One single-ended or differential (7),
2–19.
Figure 2–63
BIN
is differential) external clock output pin.
Enhanced PLL
shows global and regional clocking from the fast PLL
CLK[15..12]
CLK[7..4]
11
12
CO
) period divided by 8.
5
6
(8)
Arria GX Device Handbook, Volume 1
Fast PLL
—
2–73