DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 49

KIT DEV ARRIA GX 1AGX60N

DK-DEV-1AGX60N

Manufacturer Part Number
DK-DEV-1AGX60N
Description
KIT DEV ARRIA GX 1AGX60N
Manufacturer
Altera
Series
Arria GXr
Type
FPGAr
Datasheet

Specifications of DK-DEV-1AGX60N

Contents
Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
For Use With/related Products
1AGX60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2372

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Chapter 2: Arria GX Architecture
Adaptive Logic Modules
Figure 2–38. Register Chain within a LAB
Note to
(1) The combinational or adder logic can be used to implement an unrelated, unregistered function.
Clear and Preset Logic Control
© December 2009 Altera Corporation
Figure 2–38
:
LAB-wide signals control the logic for the register ’s clear and load/preset signals. The
ALM directly supports an asynchronous clear and preset function. The register preset
is achieved through the asynchronous load of a logic high. The direct asynchronous
preset does not require a NOT gate push-back technique. Arria GX devices support
simultaneous asynchronous load/preset and clear signals. An asynchronous clear
signal takes precedence if both signals are asserted simultaneously. Each LAB
supports up to two clears and one load/preset signal.
Combinational
Combinational
Logic
Logic
(Note 1)
adder0
adder1
adder0
adder1
reg_chain_out
reg_chain_in
D
D
D
D
reg0
reg1
reg0
reg1
From Previous ALM
Within The LAB
To Next ALM
within the LAB
Q
Q
Q
Q
To general or
To general or
To general or
To general or
To general or
To general or
To general or
To general or
Arria GX Device Handbook, Volume 1
local routing
local routing
local routing
local routing
local routing
local routing
local routing
local routing
2–43

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