DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 60

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

2–54
Figure 2–46. M-RAM Block Control Signals
Arria GX Device Handbook, Volume 1
Dedicated
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
The R4, R24, C4, and direct link interconnects from adjacent LABs on either the right
or left side drive the M-RAM block local interconnect. Up to 16 direct link input
connections to the M-RAM block are possible from the left adjacent LABs and another
16 are possible from the right adjacent LAB. M-RAM block outputs can also connect to
left and right LABs through direct link interconnect.
floorplan for the EP1AGX90 device and the location of the M-RAM interfaces.
Figure 2–48
logic array.
6
clock_a
and
clocken_a
Figure 2–49
aclr_a
renwe_a
show the interface between the M-RAM block and the
renwe_b
aclr_b
clocken_b
clock_b
Figure 2–47
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
shows an example
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
TriMatrix Memory