HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 82

• Manufacturer Part Number: HD6413008F
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
• Manufacturer: RENESAS [Renesas Technology Corp]

2. CPU
Table 2.10 Block Transfer Instruction
Instruction
EEPMOV.B
EEPMOV.W ⎯
2.6.4
The H8/300H instructions consist of 2-byte (word) units. An instruction consists of an operation
field (OP field), a register field (r field), an effective address extension (EA field), and a condition
field (cc).
Operation Field: Indicates the function of the instruction, the addressing mode, and the operation
to be carried out on the operand. The operation field always includes the first 4 bits of the
instruction. Some instructions have two operation fields.
Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers
by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.
Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement. A 24-bit address or displacement is treated as 32-bit data in which the
first 8 bits are 0 (H'00).
Condition Field: Specifies the branching condition of Bcc instructions.
Figure 2.9 shows examples of instruction formats.
Rev.4.00 Aug. 20, 2007 Page 38 of 638
REJ09B0395-0400
Basic Instruction Formats
Size
⎯
Function
if R4L ≠ 0 then
repeat
until
else next;
if R4 ≠ 0 then
repeat
until
else next;
Block transfer instruction. This instruction transfers the number of data bytes
specified by R4L or R4, starting from the address indicated by ER5, to the
location starting at the address indicated by ER6. At the end of the transfer,
the next instruction is executed.
@ER5+ → @ER6+, R4L − 1 → R4L
R4L = 0
@ER5+ → @ER6+, R4 − 1 → R4
R4 = 0