HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 183

• Manufacturer Part Number: HD6413008F
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
• Manufacturer: RENESAS [Renesas Technology Corp]

When making a transition to software standby mode, if there is contention with a bus request from
an external bus master, the BACK and strobe states may be indefinite when the transition is made.
When using software standby mode, clear the BRLE bit to 0 in BRCR before executing the
SLEEP instruction.
6.7
6.7.1
ABWCR, ASTCR, WCRH, and WCRL Write Timing: Data written to ABWCR, ASTCR,
WCRH, and WCRL takes effect starting from the next bus cycle. Figure 6.22 shows the timing
when an instruction fetched from area 0 changes area 0 from three-state access to two-state access.
DDR and CSCR Write Timing: Data written to DDR or CSCR for the port corresponding to the
CSn pin to switch between CSn output and generic input takes effect starting from the T
the DDR write cycle. Figure 6.23 shows the timing when the CS
input to CS
BRCR Write Timing: Data written to BRCR to switch between A
generic input or output takes effect starting from the T
shows the timing when a pin is changed from generic input to A
Address bus
Register and Pin Input Timing
Register Write Timing
1
φ
output.
Address bus
φ
CS
1
3-state access to area 0
T
1
Figure 6.22 ASTCR Write Timing
Figure 6.23 DDR Write Timing
T
2
High-impedance
T
3
T
1
P8DDR address
T
1
ASTCR address
3
state of the BRCR write cycle. Figure 6.24
T
T
Rev.4.00 Aug. 20, 2007 Page 139 of 638
2
2
T
23
1
3
2-state access to area 0
, A
pin is changed from generic
23
T
, A
22
3
, A
T
22
1
, A
21
, or A
21
, or A
T
20
REJ09B0395-0400
2
6. Bus Controller
output.
20
output and
3
state of