HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 26

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HD6413008F

Manufacturer Part Number
HD6413008F
Description
Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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16.2 System Control Register (SYSCR) ................................................................................... 445
16.3 Operation .......................................................................................................................... 446
Section 17 Clock Pulse Generator
17.1 Overview........................................................................................................................... 447
17.2 Oscillator Circuit............................................................................................................... 449
17.3 Duty Adjustment Circuit................................................................................................... 454
17.4 Prescalers .......................................................................................................................... 454
17.5 Frequency Divider ............................................................................................................ 454
Section 18 Power-Down State
18.1 Overview........................................................................................................................... 457
18.2 Register Configuration...................................................................................................... 459
18.3 Sleep Mode ....................................................................................................................... 464
18.4 Software Standby Mode.................................................................................................... 464
18.5 Hardware Standby Mode .................................................................................................. 468
18.6 Module Standby Function................................................................................................. 469
18.7 System Clock Output Disabling Function......................................................................... 470
Rev.4.00 Aug. 20, 2007 Page xxvi of xliv
REJ09B0395-0400
17.1.1 Block Diagram..................................................................................................... 448
17.2.1 Connecting a Crystal Resonator........................................................................... 449
17.2.2 External Clock Input............................................................................................ 451
17.5.1 Register Configuration......................................................................................... 454
17.5.2 Division Control Register (DIVCR) .................................................................... 455
17.5.3 Usage Notes ......................................................................................................... 456
18.2.1 System Control Register (SYSCR) ...................................................................... 459
18.2.2 Module Standby Control Register H (MSTCRH)................................................ 461
18.2.3 Module Standby Control Register L (MSTCRL)................................................. 462
18.3.1 Transition to Sleep Mode..................................................................................... 464
18.3.2 Exit from Sleep Mode.......................................................................................... 464
18.4.1 Transition to Software Standby Mode ................................................................. 464
18.4.2 Exit from Software Standby Mode ...................................................................... 465
18.4.3 Selection of Waiting Time for Exit from Software Standby Mode...................... 465
18.4.4 Sample Application of Software Standby Mode.................................................. 467
18.4.5 Note...................................................................................................................... 467
18.5.1 Transition to Hardware Standby Mode................................................................ 468
18.5.2 Exit from Hardware Standby Mode ..................................................................... 468
18.5.3 Timing for Hardware Standby Mode ................................................................... 468
18.6.1 Module Standby Timing ...................................................................................... 469
18.6.2 Read/Write in Module Standby............................................................................ 469
18.6.3 Usage Notes ......................................................................................................... 469
......................................................................................... 457
.................................................................................. 447

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