HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 236

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HD6413008F

Manufacturer Part Number
HD6413008F
Description
Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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8. 16-Bit Timer
8.2.5
TISRB is an 8-bit readable/writable register that indicates GRB compare match or input capture
and enables or disables GRB compare match and input capture interrupt requests.
TISRB is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Input Capture/Compare Match Interrupt Enable B2 (IMIEB2): Enables or disables
the interrupt requested by the IMFB2 when IMFB2 flag is set to 1.
Bit 6
IMIEB2
0
1
Rev.4.00 Aug. 20, 2007 Page 192 of 638
REJ09B0395-0400
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flag.
Timer Interrupt Status Register B (TISRB)
Bit
Description
IMIB2 interrupt requested by IMFB2 flag is disabled
IMIB2 interrupt requested by IMFB2 flag is enabled
Reserved bit
7
1
IMIEB2
R/W
6
0
IMIEB1
Input capture/compare match interrupt enable B2 to B0
These bits enable or disable interrupts by the IMFB flags
R/W
5
0
IMIEB0
R/W
4
0
Reserved bit
3
1
R/(W)*
IMFB2
Input capture/compare match
flags B2 to B0
Status flags indicating GRB
compare match or input capture
2
0
R/(W)*
IMFB1
1
0
R/(W)*
IMFB0
0
0
(Initial value)

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