HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 333

• Manufacturer Part Number: HD6413008F
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
• Manufacturer: RENESAS [Renesas Technology Corp]

10.2.5
NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups
1 and 0 (pins TP
specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The
address of NDRA differs depending on whether TPC output groups 0 and 1 have the same output
trigger or different output triggers.
NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by
the same compare match event, the NDRA address is H'FFFA5. The upper 4 bits belong to group
1 and the lower 4 bits to group 0. Address H'FFFA7 consists entirely of reserved bits that cannot
be modified and always read 1.
Address H'FFFA5
Address H'FFFA7
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Next Data Register A (NDRA)
7
to TP
NDR7
R/W
7
0
⎯
⎯
7
1
0
). During TPC output, when an 16-bit timer compare match event
Next data 7 to 4
These bits store the next output
data for TPC output group 1
NDR6
R/W
6
0
⎯
⎯
6
1
NDR5
R/W
5
0
⎯
⎯
5
1
10. Programmable Timing Pattern Controller (TPC)
NDR4
R/W
Reserved bits
4
0
⎯
⎯
4
1
Rev.4.00 Aug. 20, 2007 Page 289 of 638
NDR3
R/W
3
0
⎯
⎯
3
1
Next data 3 to 0
These bits store the next output
data for TPC output group 0
NDR2
R/W
2
0
⎯
⎯
2
1
NDR1
R/W
REJ09B0395-0400
1
0
⎯
⎯
1
1
NDR0
R/W
0
0
⎯
⎯
0
1