HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 239

• Manufacturer Part Number: HD6413008F
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
• Manufacturer: RENESAS [Renesas Technology Corp]

8.2.6
TISRC is an 8-bit readable/writable register that indicates 16TCNT overflow or underflow and
enables or disables overflow interrupt requests.
TISRC is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Overflow Interrupt Enable 2 (OVIE2): Enables or disables the interrupt requested by the
OVF2 when OVF2 flag is set to 1.
Bit 6
OVIE2
0
1
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flag.
Timer Interrupt Status Register C (TISRC)
Description
OVI2 interrupt requested by OVF2 flag is disabled
OVI2 interrupt requested by OVF2 flag is enabled
Bit
Reserved bit
⎯
⎯
7
1
OVIE2
R/W
6
0
Overflow interrupt enable 2 to 0
These bits enable or disable interrupts by the OVF flags
OVIE1
R/W
5
0
OVIE0
R/W
4
0
Reserved bit
Rev.4.00 Aug. 20, 2007 Page 195 of 638
⎯
⎯
3
1
R/(W)*
OVF2
Overflow flags 2 to 0
Status flags indicating
interrupts by OVF flags
2
0
R/(W)*
OVF1
1
0
REJ09B0395-0400
8. 16-Bit Timer
R/(W)*
OVF0
(Initial value)
0
0