HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 402

• Manufacturer Part Number: HD6413008F
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12. Serial Communication Interface
In transmitting serial data, the SCI operates as follows:
• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI
• After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
• The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
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REJ09B0395-0400
TDRE
TEND
recognizes that TDR contains new data, and loads this data from TDR into TSR.
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
⎯ Start bit: One 0 bit is output.
⎯ Transmit data: 7 or 8 bits are output, LSB first.
⎯ Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor
⎯ Stop bit(s): One or two 1 bits (stop bits) are output.
⎯ Mark state: Output of 1 bits continues until the start bit of the next transmit data.
loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the
next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop bit,
then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a transmit-
end interrupt (TEI) is requested at this time
Figure 12.6 shows an example of SCI transmit operation in asynchronous mode.
TXI interrupt
request
1
bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can
also be selected.
Start bit
Figure 12.6 Example of SCI Transmit Operation in Asynchronous Mode
0
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
D0
D1
1 frame
(8-Bit Data with Parity and One Stop Bit)
Data
D7
Parity
bit
0/1
TXI interrupt
request
Stop
bit
1
Start
bit
0
D0
D1
Data
D7
Parity
bit
0/1
TEI interrupt
request
Stop
bit
1
Idle state
(mark state)
1