HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 29

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HD6413008F

Manufacturer Part Number
HD6413008F
Description
Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Section 1 Overview
Figure 1.1
Figure 1.2
Section 2 CPU
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 2.5
Figure 2.6
Figure 2.7
Figure 2.8
Figure 2.9
Figure 2.10
Figure 2.11
Figure 2.12
Figure 2.13
Figure 2.14
Figure 2.15
Figure 2.16
Figure 2.17
Figure 2.18
Section 3 MCU Operating Modes
Figure 3.1
Section 4 Exception Handling
Figure 4.1
Figure 4.2
Figure 4.3
Figure 4.4
Figure 4.5
Figure 4.6
Section 5 Interrupt Controller
Figure 5.1
Figure 5.2
Block Diagram ...................................................................................................
Pin Arrangement of H8/3008 (FP-100B or TFP-100B Package, Top View) .....
CPU Operating Modes ....................................................................................... 18
Memory Map...................................................................................................... 19
CPU Registers .................................................................................................... 20
Usage of General Registers ................................................................................ 21
Stack ................................................................................................................... 22
General Register Data Formats (1) ..................................................................... 24
General Register Data Formats (2) ..................................................................... 25
Memory Data Formats........................................................................................ 26
Instruction Formats............................................................................................. 39
Memory-Indirect Branch Address Specification ................................................ 43
Processing States ................................................................................................ 47
Classification of Exception Sources ................................................................... 48
State Transitions ................................................................................................. 49
Stack Structure after Exception Handling .......................................................... 50
On-Chip Memory Access Cycle......................................................................... 52
Pin States during On-Chip Memory Access (Address Update Mode 1)............. 52
Access Cycle for On-Chip Supporting Modules ................................................ 53
Pin States during Access to On-Chip Supporting Modules ................................ 53
Memory Map of H8/3008 in Each Operating Mode........................................... 63
Exception Sources .............................................................................................. 66
Reset Sequence (Modes 1 and 3)........................................................................ 69
Reset Sequence (Modes 2 and 4)........................................................................ 70
Interrupt Sources and Number of Interrupts....................................................... 71
Stack after Completion of Exception Handling.................................................. 72
Operation when SP Value is Odd ....................................................................... 74
Interrupt Controller Block Diagram ................................................................... 76
Block Diagram of Interrupts IRQ
Figures
5
to IRQ
Rev.4.00 Aug. 20, 2007, Page xxix of xliv
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