HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 670

• Manufacturer Part Number: HD6413008F
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Appendix D Pin States
Modes 3 and 4: Figure D.2 is a timing diagram for the case in which RES goes low during an
external memory access in mode 3 or 4. As soon as RES goes low, all ports are initialized to the
input state. AS, RD, HWR, LWR, and CS
The address bus is initialized to the low output level 2.5 φ clock cycles after the low level of RES
is sampled. However, when PA
PB
low. Clock pin P6
Rev.4.00 Aug. 20, 2007 Page 626 of 638
REJ09B0395-0400
3
are used as CS output pins, they go to the high-impedance state at the same time as RES goes
P6
RES
Internal reset
signal
A
CS
AS, RD
(read)
HWR, LWR
(write)
D
(write)
I/O port,
PA
CS
20
15
7
4
0
7
/φ
/A
to A
to D
to CS
23
0
0
to PA
1
7
Figure D.2 Reset during Memory Access (Modes 3 and 4)
/φ goes to the output state at the next rise of φ after RES goes low.
6
/A
21
,
4
to PA
Access to external
T
6
1
are used as address bus pins, or when P8
0
memory
go high, and D
T
2
T
3
15
to D
0
go to the high-impedance state.
High impedance
High impedance
H'00000
3
to P8
1
and PB
0
to