HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 508

• Manufacturer Part Number: HD6413008F
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
• Manufacturer: RENESAS [Renesas Technology Corp]

18. Power-Down State
18.3
18.3.1
When the SSBY bit is cleared to 0 in SYSCR, execution of the SLEEP instruction causes a
transition from the program execution state to sleep mode. Immediately after executing the SLEEP
instruction the CPU halts, but the contents of its internal registers are retained. On-chip supporting
modules do not halt in sleep mode. Modules which have been placed in standby by the module
standby function, however, remain halted.
18.3.2
Sleep mode is exited by an interrupt, or by input at the RES or STBY pin.
Exit by Interrupt: An interrupt terminates sleep mode and causes a transition to the interrupt
exception handling state. Sleep mode is not exited by an interrupt source in an on-chip supporting
module if the interrupt is disabled in the on-chip supporting module. Sleep mode is not exited by
an interrupt other than NMI if the interrupt is masked by interrupt priority settings and the settings
of the I and UI bits in CCR, IPR.
Exit by RES Input: Low input at the RES pin exits from sleep mode to the reset state.
Exit by STBY Input: Low input at the STBY pin exits from sleep mode to hardware standby
mode.
18.4
18.4.1
To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in
SYSCR.
In software standby mode, current dissipation is reduced to an extremely low level because the
CPU, clock, and on-chip supporting modules all halt. On-chip supporting modules are reset and
halted. As long as the specified voltage is supplied, however, CPU register contents and on-chip
RAM data are retained. The settings of the I/O ports also held. When the WDT is used as a
watchdog timer (WT/IT = 1), the TME bit must be cleared to 0 before setting SSBY. Also, when
setting TME to 1, SSBY should be cleared to 0.
Clear the BRLE bit in BRCR (inhibiting bus release) before making a transition to software
standby mode.
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Transition to Sleep Mode
Exit from Sleep Mode
Sleep Mode
Software Standby Mode
Transition to Software Standby Mode