HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 231

• Manufacturer Part Number: HD6413008F
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
• Manufacturer: RENESAS [Renesas Technology Corp]

8.2.3
TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 2. It also
selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.
TMDR is initialized to H'98 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in
phase counting mode.
Bit 6
MDF
0
1
When MDF is set to 1 to select phase counting mode, 16TCNT2 operates as an up/down-counter
and pins TCLKA and TCLKB become counter clock input pins. 16TCNT2 counts both rising and
falling edges of TCLKA and TCLKB, and counts up or down as follows.
Bit
Initial value
Read/Write
Timer Mode Register (TMDR)
Description
Channel 2 operates normally
Channel 2 operates in phase counting mode
Reserved bit
⎯
⎯
7
1
Phase counting mode flag
Selects phase counting mode for channel 2
MDF
R/W
6
0
Flag direction
Selects the setting condition for the overflow
flag (OVF) in TISRC
FDIR
R/W
5
0
⎯
⎯
4
1
Reserved bit
Rev.4.00 Aug. 20, 2007 Page 187 of 638
⎯
⎯
3
1
PWM2
R/W
PWM mode 2 to 0
These bits select PWM
mode for channels 2 to 0
2
0
PWM1
R/W
REJ09B0395-0400
1
0
8. 16-Bit Timer
(Initial value)
PWM0
R/W
0
0