HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 559

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HD6413008F

Manufacturer Part Number
HD6413008F
Description
Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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A.3
The tables in this section can be used to calculate the number of states required for instruction
execution by the H8/300H CPU. Table A.4 indicates the number of instruction fetch, data
read/write, and other cycles occurring in each instruction. Table A.3 indicates the number of states
required per cycle according to the bus size. The number of states required for execution of an
instruction can be calculated from these two tables as follows:
Number of states = I × S
Examples of Calculation of Number of States Required for Execution
Examples: Advanced mode, stack located in external address space, on-chip supporting modules
accessed with 8-bit bus width, external devices accessed in three states with one wait state and
16-bit bus width.
BSET #0, @FFFFC7:8
JSR @@30
From table A.4, I = L = 2 and J = K = M = N = 0
From table A.3, S
Number of states = 2 × 4 + 2 × 3 = 14
From table A.4, I = J = K = 2 and L = M = N = 0
From table A.3, S
Number of states = 2 × 4 + 2 × 4 + 2 × 4 = 24
Number of States Required for Execution
I
+ J × S
I
I
= 4 and S
= S
J
= S
J
+ K × S
K
L
= 4
= 3
K
+ L × S
L
+ M × S
Rev.4.00 Aug. 20, 2007 Page 515 of 638
M
+ N × S
N
Appendix A Instruction Set
REJ09B0395-0400

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