HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 335

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HD6413008F

Manufacturer Part Number
HD6413008F
Description
Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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10.2.6
NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups
3 and 2 (pins TP
specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The
address of NDRB differs depending on whether TPC output groups 2 and 3 have the same output
trigger or different output triggers.
NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by
the same compare match event, the NDRB address is H'FFFA4. The upper 4 bits belong to group
3 and the lower 4 bits to group 2. Address H'FFFA6 consists entirely of reserved bits that cannot
be modified and always read 1.
Address H'FFFA4
Address H'FFFA6
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Next Data Register B (NDRB)
15
NDR15
to TP
R/W
7
0
7
1
8
). During TPC output, when an 16-bit timer compare match event
Next data 15 to 12
These bits store the next output
data for TPC output group 3
NDR14
R/W
6
0
6
1
NDR13
R/W
5
0
5
1
10. Programmable Timing Pattern Controller (TPC)
NDR12
R/W
Reserved bits
4
0
4
1
Rev.4.00 Aug. 20, 2007 Page 291 of 638
NDR11
R/W
3
0
3
1
Next data 11 to 8
These bits store the next output
data for TPC output group 2
NDR10
R/W
2
0
2
1
NDR9
R/W
REJ09B0395-0400
1
0
1
1
NDR8
R/W
0
0
0
1

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