HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 632

• Manufacturer Part Number: HD6413008F
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Appendix B Internal I/O Registers
SSR—Serial Status Register
Rev.4.00 Aug. 20, 2007 Page 588 of 638
REJ09B0395-0400
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flag.
Bit
Transmit data register empty
R/(W)*
TDRE
0
1
7
1
[Setting conditions]
[Clearing condition]
Receive data register full
R/(W)*
RDRF
0
1
6
0
[Clearing conditions] • Reset or transition to standby mode
[Setting condition]
Overrun error
0
1
[Clearing conditions] • Reset or transition to standby mode
[Setting condition]
R/(W)*
ORER
5
0
Read TDRE when TDRE = 1, then write 0 in TDRE.
• Reset or transition to standby mode
• TE is 0 in SCR.
• Data is transferred from TDR to TSR, enabling new data to be written in TDR
Framing error (for serial communication interface)
Error signal status (for smart card interface)
FER/ERS
R/(W)*
0
1
0
1
4
0
• Read RDRF when RDRF = 1, then write 0 in RDRF.
Serial data is received normally and transferred from RSR to RDR.
[Clearing conditions] • Reset or transition to standby mode
[Setting condition]
[Clearing conditions] • Reset or transition to standby mode
[Setting condition]
Parity error
0
1
• Read ORER when ORER = 1, then write 0 in ORER.
Overrun error (reception of the next serial data ends when RDRF = 1)
R/(W)*
[Clearing conditions] • Reset or transition to standby mode
[Setting condition]
PER
3
0
Transmit end (for serial communication interface)
Transmit end (for smart card interface)
Note: * etu: Elementary time unit (time required to transmit one bit)
0
1
0
1
TEND
• Read FER when FER = 1, then write 0 in FER.
Framing error (stop bit is 0)
• Read ERS when ERS = 1, then write 0 in ERS.
A low error signal is received.
R
2
1
[Clearing condition]
Read TDRE when TDRE = 1, then write 0 in TDRE.
[Setting conditions]
• Reset or transition to standby mode
• TE is cleared to 0 in SCR.
• TDRE is 1 when last bit of 1-byte serial character is
[Clearing condition]
Read TDRE when TDRE = 1, then write 0 in TDRE.
[Setting conditions]
• Reset or transition to standby mode
• TE is cleared to 0 in SCR and FER/ERS is cleared to 0.
• TDRE is 1 and FER/ERS is 0 (normal transmission)
transmitted.
2.5 etu* (when GM = 0) or 1.0 etu (when GM = 1) after
1-byte serial character is transmitted.
• Read PER when PER = 1, then write 0 in PER.
Parity error (parity of receive data does not match parity
setting of O/E bit in SMR)
H'FFFB4
MPB
Multiprocessor bit
R
1
0
0
1
Multiprocessor bit transfer
Multiprocessor bit value in receive data is 0
Multiprocessor bit value in receive data is 1
0
1
Multiprocessor bit value in transmit data is 0
Multiprocessor bit value in transmit data is 1
MPBT
R/W
0
0
SCI0