HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 165

• Manufacturer Part Number: HD6413008F
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Address Update Mode 1: Address update mode 1 is compatible with the previous H8/300H
Series. Addresses are always updated between bus cycles.
Address Update Mode 2: In address update mode 2, address updating is performed only in
external space accesses. In this mode, the address can be retained between an external space read
cycle and an instruction fetch cycle (on-chip memory) by placing the program in on-chip memory.
Address update mode 2 is therefore useful when connecting a device that requires address hold
time with respect to the rise of the RD strobe.
Switching between address update modes 1 and 2 is performed by means of the ADRCTL bit in
ADRCR. The initial value of ADRCR is the address update mode 1 setting, providing
compatibility with the previous H8/300H Series.
Cautions: The address output methods are designed so that the initial state with the bit selection
method is compatible with the H8/3062F-ZTAT (HD64F3062) (i.e. address update mode 1).
However, the following points should be noted.
• ADRCR is allocated to address H'FEE01E. In the H8/3062F-ZTAT, the corresponding address
• When address update mode 2 is selected, the address in an internal space (on-chip memory or
• In order to secure address holding with respect to the rise of RD, when address update mode 2
Figure 6.6 Example of Consecutive External Space Accesses in Address Update Mode 2
is empty space, but it is necessary to confirm that no accesses are made to H'FEE01E in the
program.
internal I/O) access cycle is not output externally.
is used an external space read access must be completed within a single access cycle. For
example, in a word access to 8-bit access space, the bus cycle is split into two as shown in
figure 6.6, and so there is not a single access cycle. In this case, address holding is not
guaranteed at the rise of RD between the first (even address) and second (odd address) access
cycles (area inside the ellipse in the figure).
Address update
mode 2
RD
memory cycle
On-chip
Even address
(8-bit space word access)
External read cycle
Rev.4.00 Aug. 20, 2007 Page 121 of 638
Odd address
memory cycle
REJ09B0395-0400
6. Bus Controller
On-chip