HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 491
HD6413008F
Manufacturer Part Number
HD6413008F
Description
Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6413008F.pdf
(686 pages)
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17.1
The H8/3008 has a built-in clock pulse generator (CPG) that generates the system clock (φ) and
other internal clock signals (φ/2 to φ/4096). After duty adjustment, a frequency divider divides the
clock frequency to generate the system clock (φ). The system clock is output at the φ pin*
furnished as a master clock to prescalers that supply clock signals to the on-chip supporting
modules. Frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the frequency
divider by settings in a division control register (DIVCR)*
reduced in almost direct proportion to the frequency division ratio.
Notes: 1. Usage of the φ pin differs depending on the chip operating mode and the PSTOP bit
2. The division ratio of the frequency divider can be changed dynamically during
Overview
setting in the module standby control register (MSTCR). For details, see section 18.7,
System Clock Output Disabling Function.
operation. The clock output at the φ pin also changes when the division ratio is
changed. The frequency output at the φ pin is shown below.
where, EXTAL: Frequency of crystal resonator or external clock signal
φ = EXTAL × n
n:
Section 17 Clock Pulse Generator
Frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8)
Rev.4.00 Aug. 20, 2007 Page 447 of 638
2
. Power consumption in the chip is
17. Clock Pulse Generator
REJ09B0395-0400
1
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