h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 434
h8s-2172
Manufacturer Part Number
h8s-2172
Description
Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2172.pdf
(570 pages)
- Current page: 434 of 570
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SCI Interface Setting by Host: When boot mode is initiated, this LSI measures the low period of
asynchronous SCI-communication data (H'00), which is transmitted consecutively by the host.
The SCI transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates
the bit rate of transmission by the host by means of the measured low period and transmits the bit
adjustment end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment
end sign (H'00) has been received normally and transmits 1 byte of H'55 to this LSI. When
reception is not executed normally, boot mode is initiated again (reset) and the operation described
above must be executed. The bit rate between the host and this LSI is not matched by the bit rate
of transmission by the host and system clock frequency of this LSI. To operate the SCI normally,
the transfer bit rate of the host must be set to 4,800 bps, 9,600 bps, or 19,200 bps.
The system clock frequency, which can automatically adjust the transfer bit rate of the host and
the bit rate of this LSI, is shown in table 14.7. Boot mode must be initiated in the range of this
system clock.
Rev. 2.00, 03/04, page 402 of 534
tool and program
programming
Boot
Host
data
Start
bit
Figure 14.7 Automatic-Bit-Rate Adjustment Operation of SCI
D0
Figure 14.6 System Configuration in Boot Mode
Measure low period (9 bits) (data is H'00)
Control command, program data
D1
Reply response
D2
D3
D4
analysis execution
Control command,
software (on-chip)
RxD0
TxD0
D5
On-chip SCI
D6
This LSI
D7
On-chip RAM
High period of
at least 1 bit
Stop bit
memory
Flash
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