h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 227

• Manufacturer Part Number: h8s-2172
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
• Manufacturer: Renesas Electronics Corporation.

DREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
DMMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the DREQ pin while acceptance via the DREQ pin is possible, the
request is held within the DMAC. Then when activation is initiated within the DMAC, the request
is cleared. At the end of the write cycle, acceptance resumes and DREQ pin low level sampling is
performed again; this sequence of operations is repeated until the end of the transfer.
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in DMAC.
[3], [6] DMA cycle is started.
[4], [7] Acceptance is resumed after completion of dead cycle.
Figure 7.23 Example of Block Transfer Mode Transfer Activated by DREQ Pin Low Level
φ
Address bus
DMA control
Channel
Acceptance after transfer enabling;
(As in [1],
Idle
[1]
Minimum 3 cycles
Request
Bus release
pin low level is sampled at rise of φ, and request is held.)
[2]
Read
Request clearance period
[3]
Transfer source
DMA read
One block transfer
Write
DMA write
destination
pin low level is sampled at rise of φ, and request is held.
Transfer
Idle
Acceptance
resumed
[4]
Minimum 3 cycles
Request
Bus release
[5]
Rev. 2.00, 03/04, page 195 of 534
Read
Request clearance period
[6]
Transfer source
DMA read
One block transfer
Write
DMA write
destination
Transfer
Idle
Acceptance
resumed
[7]
Bus release