h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 367

• Manufacturer Part Number: h8s-2172
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
• Manufacturer: Renesas Electronics Corporation.

Bit
5
4
3, 2
1
0
Bit Name
EP2CLR
EP1CLR

EP0oCLR
EP0iCLR
Initial
Value
0
0
All 0
0
0
R/W
W
R
W
W
W
W
R
Description
EP2 Clear
1 is written when clearing EP2 IN FIFO. Writing 0 is
invalid and no operation is performed.
EP2 FIFO Clear Status
[Setting condition]
This bit is set to 1 when the EP2 FIFO is forcibly cleared
by the FCLR register. When this bit is set to 1, access to
the EP2 FIFO is prohibited. This bit is cleared to 0
automatically after the FIFO is internally cleared. Confirm
that this bit is cleared to 0 and then wait for at least four
cycles, before accessing to the EP2.
[Clearing condition]
This bit cannot be cleared because this bit is a status bit.
EP1 Clear
1 is written when clearing EP1 OUT FIFO. Writing 0 is
invalid and no operation is performed.
Reserved
The write value should always be 0.
EP0o Clear
1 is written when clearing EP0o OUT FIFO. Writing 0 is
invalid and no operation is performed.
EP0i Clear
1 is written when clearing EP0i IN FIFO. Writing 0 is
invalid and no operation is performed.
EP0i FIFO Clear Status
[Setting condition]
This bit is set to 1 when the EP0i FIFO is forcibly cleared
by the FCLR register. When this bit is set to 1, access to
the EP0i FIFO is prohibited. This bit is cleared to 0
automatically after the FIFO is internally cleared. Confirm
that this bit is cleared to 0 and then wait for at least four
cycles, before accessing to the EP0i.
[Clearing condition]
This bit cannot be cleared because this bit is a status bit.
Rev. 2.00, 03/04, page 335 of 534