h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 11
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h8s-2172
Manufacturer Part Number
h8s-2172
Description
Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2172.pdf
(570 pages)
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5.7
Section 6 Bus Controller (BSC).........................................................................83
6.1
6.2
6.3
6.4
6.5
6.6
5.6.2
5.6.3
5.6.4
Usage Notes ...................................................................................................................... 81
5.7.1
5.7.2
5.7.3
Features............................................................................................................................. 83
Input/Output Pins .............................................................................................................. 85
Register Descriptions ........................................................................................................ 86
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10 Refresh Time Constant Register (RTCOR) ......................................................... 101
Bus Control ....................................................................................................................... 102
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
Basic Bus Interface ........................................................................................................... 109
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
DRAM Interface ............................................................................................................... 122
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
6.6.7
Interrupt Control Mode 1 ..................................................................................... 76
Interrupt Exception Handling Sequence .............................................................. 78
Interrupt Response Times .................................................................................... 80
Conflict between Interrupt Generation and Disabling ......................................... 81
Instructions that Disable Interrupts ...................................................................... 82
Interrupts during Execution of EEPMOV Instruction.......................................... 82
Access Control Register (ACSCR) ...................................................................... 87
CS Assertion Period Control Register (CSACR)................................................. 88
Wait Control Register (WTCR) ........................................................................... 90
Bus Control Register (BCR) ................................................................................ 92
Read Strobe Timing Control Register (RDNCR) ................................................ 93
DRAM Control Register (DRAMCR) ................................................................. 94
DRAM Access Control Register (DRACCR)...................................................... 97
Refresh Control Register (REFCR) ..................................................................... 98
Refresh Timer Counter (RTCNT)........................................................................ 101
Area Division....................................................................................................... 102
Address Map ........................................................................................................ 103
Bus Specifications................................................................................................ 105
Memory Interfaces............................................................................................... 107
Chip Select Signals .............................................................................................. 108
Data Size and Data Alignment............................................................................. 109
Valid Strobes ....................................................................................................... 110
Basic Timing........................................................................................................ 110
Wait Control ........................................................................................................ 119
Read Strobe (RD) Timing.................................................................................... 120
Extension of Chip Select (CS) Assertion Period.................................................. 121
Setting DRAM Space........................................................................................... 122
Address Multiplexing .......................................................................................... 122
Data Bus............................................................................................................... 123
Pins Used for DRAM Interface............................................................................ 123
Basic Timing........................................................................................................ 124
Column Address Output Cycle Control ............................................................... 125
Row Address Output State Control...................................................................... 126
Rev. 2.00, 03/04, page xi of xxxii
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