h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 368

• Manufacturer Part Number: h8s-2172
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
• Manufacturer: Renesas Electronics Corporation.

12.3.17 Endpoint Stall Register 0 (EPSTL0)
EPSTL0 is used to stall each endpoint. When 1 is written in a bit, the corresponding endpoint
returns a stall handshake to the host, following from the next transfer. The stall bit for endpoint 0
is cleared automatically on reception of 8-byte request data for which decoding is performed by
the function, and thus the EP0 STL bit is cleared to 0. When the SETUP TS flag in IFR0 is set to
1, a write of 1 to the EP0 STL bit is ignored. For details, refer to section 12.5.8, Stall Operations.
When the ASCE bit in CTRL is set to 1, the EPxSTL (x = 0, 1, 2, 3) bit is automatically cleared.
For details, refer to section 12.3.19, Control Register (CTRL).
12.3.18 DMA Set Register 0 (DMA0)
DMA0 is set when the DMAC dual address transfer is used for data registers for endpoints 1 and
2.
For endpoint 1, if 1 is written in the EP1 DMAE bit, the transfer is requested to the DMAC when
the EP1 FIFO is full at least in the single FIFO. That is, when there is valid receive data in the
FIFO, the transfer is requested to the DMAC. When all receive data is read and both FIFOs are
empty, the transfer is not requested to the DMCA any more.
For endpoint 2, if 1 is written in the EP2 DMAE bit, the transfer is requested to the DMAC when
the EP2 FIFO is empty at least in the single FIFO. That is, when there is no valid data in the FIFO
even with one side, the transfer is requested to the DMAC. When data is written by the
microcomputer and both FIFOs are full, the transfer is not requested to the DMCA any more.
Since an interrupt request is not masked automatically, the EP1 FULL and EP2 EMPTY bits in
IER0 are cleared to 0 and an interrupt should not be requested by an interrupt pin.
Rev. 2.00, 03/04, page 336 of 534
Bit
31 to 4 
3
2
1
0
Bit Name
EP3STL
EP2STL
EP1STL
EP0STL
Initial
Value
All 0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
Description
Reserved
The write value should always be 0.
EP3 Stall
Sets the EP3 stall state.
EP2 Stall
Sets the EP2 stall state.
EP1 Stall
Sets the EP1 stall state.
EP0 Stall
Sets the EP0 stall state.