h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 55
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h8s-2172
Manufacturer Part Number
h8s-2172
Description
Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2172.pdf
(570 pages)
- Current page: 55 of 570
- Download datasheet (5Mb)
2.4.2
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched for read, the least significant PC bit is regarded as 0.)
2.4.3
EXR is an 8-bit register that can be operated by the LDC, STC, ANDC, ORC, and XORC
instructions. When an instruction other than STC is executed, all interrupts including NMI are
masked in three states after the instruction is completed.
Bit
7
6 to3
2 to 0
Bit Name
T
I2
I1
I0
Program Counter (PC)
Extended Control Register (EXR)
Initial
Value
0
All1
1
1
1
SP (ER7)
R/W
R/W
R/W
R/W
R/W
Figure 2.8 Stack
Description
Trace Bit
When this bit is set to 1, trace exception processing
starts every when an instruction is executed. When
this bit is cleared to 0, instructions are consecutively
executed.
Reserved
These bits are always read as 1.
Interrupt Mask Bits 2 to 0
Specify interrupt request mask levels (0 to 7). In this
LSI, these bits cannot be used as the interrupt mask
level.
Rev. 2.00, 03/04, page 23 of 534
Stack area
Free area
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