h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 248

• Manufacturer Part Number: h8s-2172
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
• Manufacturer: Renesas Electronics Corporation.

7.6
Usage Notes
DMAC Register Access during Operation: Except for clearing the DA bit to 0 in DMMDR,
settings should not be changed for a channel in operation (including the transfer standby state).
Transfer must be disabled before changing a setting for an operational channel.
Module Stop State: When the DMACKSTP bit is set to 1 in MSTPCR, the DMAC clock stops
and the DMAC enters the module stop state. However, 1 cannot be written to the DMACKSTP bit
when any of the DMAC's channels is enabled for transfer, or when an interrupt is being requested.
Before setting the DMACKSTP bit, first clear the DA bit in DMMDR to 0, then clear the IRF or
DIE bit in DMMDR to 0.
When the DMAC clock stops, DMAC registers can no longer be accessed. The following DMAC
register settings remain valid in the module stop state, and so should be changed, if necessary,
before making the module stop transition.
• TENDE = 1 in DMMDR (TEND pin enable)
• DRAKE = 1 in DMMDR (DRAK pin enable)
• AMS = 1 in DMMDR (DACK pin enable)
DREQ Pin Falling Edge Activation: Falling edge sensing on the DREQ pin is performed in
synchronization with DMAC internal operations, as indicated below.
[1] Activation request standby state: Waits for low level sensing on DREQ pin, then goes to [2].
[2] Transfer standby state: Waits for DMAC data transfer to become possible, then goes to [3].
[3] Activation request disabled state: Waits for high level sensing on DREQ pin, then goes to [1].
After DMAC transfer is enabled, the DMAC goes to state [1], so low level sensing is used for the
initial activation after transfer is enabled.
Activation Source Acceptance: At the start of activation source acceptance, low level sensing is
used for both falling edge sensing and low level sensing on the DREQ pin. Therefore, a request is
accepted in the case of a low level at the DREQ pin that occurs before execution of the DMMDR
write for setting the transfer-enabled state.
When the DMAC is activated, make sure, if necessary, that a low level does not remain at the
DREQ pin from the previous end of transfer, etc.
Enabling Interrupt Requests when IRF = 1 in DMMDR: When transfer is started while the IRF
bit is set to 1 in DMMDR, if the DIE bit is set to 1 in DMMDR together with the DA bit in
DMMDR, enabling interrupt requests, an interrupt will be requested since DIE = 1 and IRF = 1.
To prevent the occurrence of an erroneous interrupt request when transfer starts, ensure that the
IRF bit is cleared to 0 before the DIE bit is set to 1.
Rev. 2.00, 03/04, page 216 of 534