h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 15

• Manufacturer Part Number: h8s-2172
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 10 Watchdog Timer (WDT)..................................................................283
10.1 Features............................................................................................................................. 283
10.2 Register Descriptions ........................................................................................................ 284
10.3 Operation .......................................................................................................................... 286
10.4 Interrupt Sources............................................................................................................... 288
10.5 Usage Notes ...................................................................................................................... 289
Section 11 Serial Communication Interface for Boot Mode (SCI) ...................291
11.1 Features............................................................................................................................. 291
11.2 Input/Output Pins .............................................................................................................. 292
11.3 Register Descriptions ........................................................................................................ 293
11.4 Operation in Asynchronous Mode .................................................................................... 304
11.5 Interrupt Sources............................................................................................................... 314
11.6 Usage Notes ...................................................................................................................... 315
10.2.1 Timer Counter (TCNT)........................................................................................ 284
10.2.2 Timer Control/Status Register (TCSR)................................................................ 284
10.3.1 Watchdog Timer Mode ........................................................................................ 286
10.3.2 Interval Timer Mode............................................................................................ 287
10.3.3 Watchdog Timer Overflow Flag (OVF) Timing.................................................. 288
10.5.1 Notes on Register Access..................................................................................... 289
10.5.2 Conflict between Timer Counter (TCNT) Write and Increment.......................... 290
10.5.3 Changing Values of CKS2 to CKS0 Bits............................................................. 290
10.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 290
11.3.1 Receive Shift Register (RSR) .............................................................................. 293
11.3.2 Receive Data Register (RDR) .............................................................................. 293
11.3.3 Transmit Data Register (TDR)............................................................................. 293
11.3.4 Transmit Shift Register (TSR) ............................................................................. 294
11.3.5 Serial Mode Register (SMR) ............................................................................... 294
11.3.6 Serial Control Register (SCR) ............................................................................. 295
11.3.7 Serial Status Register (SSR) ................................................................................ 297
11.3.8 Bit Rate Register (BRR) ...................................................................................... 300
11.4.1 Data Transfer Format........................................................................................... 305
11.4.2 Receive Data Sampling Timing and Reception Margin in
11.4.3 Clock.................................................................................................................... 307
11.4.4 SCI Initialization (Asynchronous Mode) ............................................................. 307
11.4.5 Data Transmission (Asynchronous Mode)........................................................... 308
11.4.6 Serial Data Reception (Asynchronous Mode)...................................................... 310
11.5.1 Interrupts in Normal Serial Communication Interface Mode .............................. 314
11.6.1 Module Stop Mode Setting .................................................................................. 315
11.6.2 Relation between Writes to TDR and the TDRE Flag ......................................... 315
11.6.3 Operation in Case of Mode Transition................................................................. 315
Asynchronous Mode ............................................................................................ 306
Rev. 2.00, 03/04, page xv of xxxii