h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 153

• Manufacturer Part Number: h8s-2172
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
• Manufacturer: Renesas Electronics Corporation.

6.5.6
Some external I/O devices require a setup time and hold time between address and CS signals and
strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR register to insert
states in which only the CS, AS, and address signals are asserted before and after a basic bus space
access cycle. Extension of the CS assertion period can be set for individual areas. With the CS
assertion extension period in write access, the data setup and hold times are less stringent since the
write data is output to the data bus.
Figure 6.21 shows an example of the timing when the CS assertion period is extended in basic bus
3-state access space.
Both extension state T
basic bus cycle, or only one of these, can be specified for individual areas. Insertion or non-
insertion can be specified for the T
register, and for the T
Read
(when
RDNn = 0)
Write
Note: n = 3 to 0
Figure 6.21 Example of Timing when Chip Select Assertion Period is Extended
Extension of Chip Select (CS) Assertion Period
φ
Address bus
Data bus
Data bus
t
,
h
state with the lower 4 bits (CSXT3 to CSXT0).
inserted before the basic bus cycle and extension state T
h
state with the upper 4 bits (CSXH3 to CSXH0) in the CSACR
T
h
T
1
Bus cycle
T
Write data
2
Rev. 2.00, 03/04, page 121 of 534
Read data
T
3
t
inserted after the
T
t