h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 397

• Manufacturer Part Number: h8s-2172
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
• Manufacturer: Renesas Electronics Corporation.

12.8.6
When data registers in this module are read from or written to, the following must be noted:
1. Receive Data Register
2. Transmit Data Register
12.8.7
EP0 interrupt sources assigned to bits 3 to 0 in IFR0 must be assigned to the same interrupt signal
by setting ISR0. There are no other restrictions on interrupt sources.
12.8.8
This module operates in high-speed or full-speed mode. The FIFO size to be used in each mode is
shown below. Therefore, data more than 64 bytes cannot be read from or written to the one FIFO
for EP1 or EP2 in full-speed mode. If the read or write is performed, correct transfer is impossible.
Data less than 64 bytes should be read from or written to.
Receive data registers must not read a data size that is greater than the effective size of the read
data item. In other words, receive data registers must not read data with data size larger than
that specified by the receive data size register. For the receive data register of EP1 having a
dual-FIFO configuration, data to be read at any time must be within the maximum packet size.
Make sure to confirm that the EP1 FULL bit in IFR0 is set to 1 before reading from data from
a single FIFO, because data registers cannot be accessed while FIFOs are switched.
Data to be written to the transmit data registers must be within the maximum packet size. For
the transmit data register of EP2 having a dual-FIFO configuration, data to be written at any
time must be within the maximum packet size. In this case, after a data write, the FIFO is
switched to the other FIFO, enabling an further data write, when the number of transmit data is
written in PKTE2. Accordingly, data of size corresponding to two FIFOs must not be written
to the transmit data registers at a time. Make sure to confirm that the EP2EMPTY bit in IFR0
is set to 1 before writing data to a single FIFO, because data registers cannot be accessed while
FIFOs are switched.
Data Register Overread or Overwrite
EP0 Interrupt Sources Assignment
FIFO Size at Full Speed Mode
Rev. 2.00, 03/04, page 365 of 534