h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 78
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h8s-2172
Manufacturer Part Number
h8s-2172
Description
Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2172.pdf
(570 pages)
- Current page: 78 of 570
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2.8
The H8S/2000 CPU has four main processing states: the reset state, exception handling state,
program execution state, and program stop state. Figure 2.13 indicates the state transitions.
• Reset state
• Exception-handling state
• Program execution state
• Program stop state
Rev. 2.00, 03/04, page 46 of 534
In this state the CPU and internal peripheral modules are all initialized and stopped. When the
RES input goes low, all current processing stops and the CPU enters the reset state. All
interrupts are masked in the reset state. Reset exception handling starts when the RES signal
changes from low to high. For details, refer to section 4, Exception Handling.
The reset state can also be entered by a watchdog timer overflow.
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception vector table and branches to that
address. For further details, refer to section 4, Exception Handling.
In this state the CPU executes program instructions in sequence.
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details,
refer to section 16, Power-Down Modes.
Processing States
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