h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 560
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h8s-2172
Manufacturer Part Number
h8s-2172
Description
Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2172.pdf
(570 pages)
- Current page: 560 of 570
- Download datasheet (5Mb)
Rev. 2.00, 03/04, page 528 of 534
Item
12.5.3 Control Transfer
Figure 12.6 Data Stage
Operation (Control-In)
12.5.3 Control Transfer
Figure 12.9 Status Stage
Operation (Control-Out)
12.5.5 EP2 Bulk-In
Transfer (Dual FIFO)
Figure 12.11 EP2 Bulk-In
Transfer Operation
12.8.11 EPDR0s Read
Page
345
348
352
366
Revisions (See Manual for Details)
Description added
Description added
Description amended
Description deleted
EPDR0s must be read in 8-byte units. If read is suspended,
data received in the next setup cannot be read normally.
Write 0 to packet enable register 0i
prohibited (EP0i TR in IER0 = 0)
EP0i transfer request interrupt
data bytes to packet enable
Write number of transmit
Write data to EP0i data
register 0i (PKTE0i)
(EP0i TR in IFR0 = 0)
register (EPDR0i)
Clear interrupt flag
every packet.
(PKTE0i)
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