h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 231

• Manufacturer Part Number: h8s-2172
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
• Manufacturer: Renesas Electronics Corporation.

DREQ Pin Falling Edge Activation Timing: Figure 7.30 shows an example of single address
mode transfer activated by the DREQ pin falling edge.
DREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
DMMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the DREQ pin while acceptance via the DREQ pin is possible, the
request is held within the DMAC. Then when activation is initiated within the DMAC, the request
is cleared, and DREQ pin high level sampling for edge sensing is started. If DREQ pin high level
sampling is completed by the end of the DMA single cycle, acceptance resumes after the end of
the single cycle, and DREQ pin low level sampling is performed again; this sequence of
operations is repeated until the end of the transfer.
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in DMAC.
[3], [6] DMA cycle start;
[4], [7] When
Acceptance after transfer enabling;
(As in [1],
φ
Address bus
DMA control
Channel
Figure 7.30 Example of Single Address Mode Transfer Activated
pin high level has been sampled, acceptance is resumed after completion of single cycle.
pin low level is sampled at rise of φ, and request is held.)
Idle
[1]
Minimum 3 cycles
pin high level sampling is started at rise of φ.
Request
Bus release
by DREQ Pin Falling Edge
[2]
clearance period
Single
[3]
Request
DMA single
Transfer source/
pin low level is sampled at rise of φ, and request is held.
destination
Idle
Acceptance
resumed
[4]
Minimum 3 cycles
Request
Bus release
[5]
clearance period
Rev. 2.00, 03/04, page 199 of 534
Single
[6]
Request
Transfer source/
DMA single Bus release
destination
Idle
Acceptance
resumed
[7]