h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 320

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h8s-2172

Manufacturer Part Number
h8s-2172
Description
Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
10.3.3
When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the
RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. The timing is
shown in figure 10.5.
10.4
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is
generated by an overflow.
Table 10.1 WDT Interrupt Source
Rev. 2.00, 03/04, page 288 of 534
Name
WOVI
Overflow signal
(internal signal)
φ
TCNT
OVF
Internal reset
signal
Watchdog Timer Overflow Flag (OVF) Timing
Interrupt Sources
Interrupt Source
TCNT overflow
Figure 10.5 Output Timing of OVF
H'FF
Interrupt Flag
OVF
H'00
518 states

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