h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 17
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h8s-2172
Manufacturer Part Number
h8s-2172
Description
Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2172.pdf
(570 pages)
- Current page: 17 of 570
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12.8 Usage Notes ...................................................................................................................... 364
Section 13 RAM ................................................................................................371
Section 14 Flash Memory (0.18-µm F-ZTAT Version) ....................................373
14.1 Features............................................................................................................................. 373
14.2 Input/Output Pins .............................................................................................................. 381
14.3 Register Descriptions ........................................................................................................ 381
14.4 On-Board Programming Mode ......................................................................................... 401
14.5 Protection .......................................................................................................................... 428
14.6 Switching between User MAT and User Boot MAT ........................................................ 431
12.8.1 Setup Data Reception........................................................................................... 364
12.8.2 FIFO Clear ........................................................................................................... 364
12.8.3 Operating Frequency............................................................................................ 364
12.8.4 Interrupts.............................................................................................................. 364
12.8.5 Register Access Size ............................................................................................ 364
12.8.6 Data Register Overread or Overwrite .................................................................. 365
12.8.7 EP0 Interrupt Sources Assignment ...................................................................... 365
12.8.8 FIFO Size at Full Speed Mode............................................................................. 365
12.8.9 Level Shifter for VBUS Pin................................................................................. 366
12.8.10 USB 2.0 Transceiver (Physical Layer) ................................................................ 366
12.8.11 EPDR0s Read ...................................................................................................... 366
12.8.12 USB Bus Idle in High-Speed Mode..................................................................... 366
12.8.13 Note on USB Bus Disconnection......................................................................... 367
12.8.14 Example of External Circuit ................................................................................ 367
12.8.15 External Physical Layer LSI ................................................................................ 368
12.8.16 Operation at the Bus Reset Reception.................................................................. 368
12.8.17 Usage Notes in Control IN Transfer .................................................................... 369
12.8.18 USB Interrupt During Software Standby ............................................................. 369
14.1.1 Operating Mode ................................................................................................... 375
14.1.2 Mode Comparison................................................................................................ 376
14.1.3 Flash MAT Configuration.................................................................................... 377
14.1.4 Block Division ..................................................................................................... 378
14.1.5 Programming/Erasing Interface ........................................................................... 379
14.3.1 Programming/Erasing Interface Register............................................................. 382
14.3.2 Programming/Erasing Interface Parameter .......................................................... 391
14.4.1 Boot Mode ........................................................................................................... 401
14.4.2 User Program Mode............................................................................................. 405
14.4.3 User Boot Mode................................................................................................... 415
14.4.4 Procedure Program and Storable Area for Programming Data ............................ 418
14.5.1 Hardware Protection ............................................................................................ 428
14.5.2 Software Protection.............................................................................................. 429
14.5.3 Error Protection.................................................................................................... 429
Rev. 2.00, 03/04, page xvii of xxxii
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