h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 215

• Manufacturer Part Number: h8s-2172
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
• Manufacturer: Renesas Electronics Corporation.

correct values may not be read if the upper and lower words are read separately. In a longword
access, the DMAC buffers the DMDAR value to ensure that the correct value is output.
Do not write to DMDAR for a channel on which a transfer operation is in progress.
DMA Transfer Count Register (DMTCR): When a DMA transfer is performed, the value in
DMTCR is decremented by 1. However, when the DMTCR value is 0, transfers are not counted
and the DMTCR value does not change.
DMTCR functions differently in block transfer mode. The upper 8 bits, DMTCR23 to DMTCR16,
are used to specify the block size, and their value does not change. The lower 16 bits, DMTCR15
to DMTCR0, function as a transfer counter, the value of which is decremented by 1 when a DMA
transfer is performed. However, when the DMTCR15 to DMTCR0 value is 0, transfers are not
counted and the DMTCR15 to DMTCR0 value does not change.
In normal transfer mode, all of the lower 24 bits of DMTCR may change, so when DMTCR is
read by the CPU during DMA transfer, a longword access must be used. During a transfer
operation, DMTCR may be updated without regard to accesses from the CPU, and the correct
values may not be read if the upper and lower words are read separately. In a longword access, the
DMAC buffers the DMTCR value to ensure that the correct value is output.
In block transfer mode, the upper 8 bits are never updated, so there is no problem with using word
access. Do not write to DMTCR for a channel on which a transfer operation is in progress. If there
is contention between an address update associated with DMA transfer and a write by the CPU,
the CPU write has priority.
In the event of contention between an DMTCR update from 1 to 0 and a write (of a nonzero value)
by the CPU, the CPU write value has priority as the DMTCR value, but transfer is terminated.
Transfer does not end if the CPU writes 0 to DMTCR.
Figure 7.11 shows DMTCR update operations in normal transfer mode and block transfer mode.
Rev. 2.00, 03/04, page 183 of 534