h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 158

• Manufacturer Part Number: h8s-2172
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
• Manufacturer: Renesas Electronics Corporation.

6.6.7
If the RAST bit is set to 1 in DRAMCR, the RAS signal goes low from the beginning of the T
state, and the row address hold time and DRAM read access time are changed relative to the fall of
the RAS signal. Use the optimum setting according to the DRAM connected and the operating
frequency of this LSI. Figure 6.24 shows an example of the timing when the RAS signal goes low
from the beginning of the T
If a row address hold time or read access time is necessary, making a setting in bits RCD1 and
RCD0 in DRACCR allows from one to three T
to be inserted between the T
the column address is output. Use the setting that gives the optimum row address signal hold time
relative to the falling edge of the RAS signal according to the DRAM connected and the operating
frequency of this LSI. Figure 6.25 shows an example of the timing when one T
Rev. 2.00, 03/04, page 126 of 534
Figure 6.24 Example of Access Timing when RAS Signal Goes Low from Beginning
Read
Write
Row Address Output State Control
φ
Address bus
Data bus
Data bus
(
(
(
(
(
,
)
)
)
)
)
r
r
state.
cycle, in which the RAS signal goes low, and the T
of T
T
p
Row address
r
State (CAST = 0)
rw
states, in which row address output is maintained,
T
r
High
High
T
c1
Column address
T
c2
rw
c1
state is set.
cycle, in which
r