h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 27

• Manufacturer Part Number: h8s-2172
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 14.26 Erasure Sequence .................................................................................................. 454
Section 15 Clock Pulse Generator
Figure 15.1 Block Diagram of Clock Pulse Generator ............................................................... 463
Figure 15.2 Connection of Crystal Resonator (Example)........................................................... 464
Figure 15.3 Crystal Resonator Equivalent Circuit ...................................................................... 464
Figure 15.4 External Clock Input (Examples) ............................................................................ 465
Figure 15.5 External Clock Input Timing................................................................................... 465
Figure 15.6 Timing of External Clock Output Stabilization Delay Time ................................... 466
Figure 15.7 Note on Board Design for Oscillation Circuit ......................................................... 467
Section 16 Power-Down Modes
Figure 16.1 Mode Transitions..................................................................................................... 471
Figure 16.2 Software Standby Mode Application Example ....................................................... 476
Figure 16.3 Hardware Standby Mode Timing ............................................................................ 477
Section 18 Electrical Characteristics
Figure 18.1 Sample of Dalington Transistor Drive Circuit......................................................... 500
Figure 18.2 Output Load Circuit................................................................................................. 501
Figure 18.3 System Clock Timing .............................................................................................. 502
Figure 18.4 Oscillation Stabilization Timing (1) ........................................................................ 502
Figure 18.5 Oscillation Stabilization Timing (2) ........................................................................ 502
Figure 18.6 Reset Input Timing.................................................................................................. 503
Figure 18.7 Interrupt Input Timing............................................................................................. 503
Figure 18.8 Basic Bus Timing: Two-State Access ..................................................................... 506
Figure 18.9 Basic Bus Timing: Three-State Access ................................................................... 507
Figure 18.10 Basic Bus Timing: Two-State Access (CS Assertion Period Extended) ............... 508
Figure 18.11 Basic Bus Timing: Three-State Access (CS Assertion Period Extended) ............. 509
Figure 18.12 DRAM Access Timing: Two-State Access ........................................................... 510
Figure 18.13 DRAM Access Timing: Two-State Burst Access ................................................. 511
Figure 18.14 DRAM Access Timing: Three-State Access (RAST = 1) ..................................... 512
Figure 18.15 DRAM Access Timing: Three-State Burst Access ............................................... 513
Figure 18.16 CAS-Before-RAS Refresh Timing......................................................................... 514
Figure 18.17 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion) ........................... 514
Figure 18.18 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0) ............. 514
Figure 18.19 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1) ............. 515
Figure 18.20 DMAC Single Address Transfer Timing: Two-State Access................................ 516
Figure 18.21 DMAC Single Address Transfer Timing: Three-State Access.............................. 517
Figure 18.22 DMAC, TEND Output Timing.............................................................................. 517
Figure 18.23 DMAC, DREQ Input Timing ................................................................................ 518
Figure 18.24 I/O Port Input/Output Timing................................................................................ 519
Figure 18.25 8-Bit Timer Output Timing ................................................................................... 519
Figure 18.26 8-Bit Timer Clock Input Timing ........................................................................... 519
Figure 18.27 8-Bit Timer Reset Input Timing ............................................................................ 519
Rev. 2.00, 03/04, page xxvii of xxxii