r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 472

• Manufacturer Part Number: r4f2456
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 8 EXDMA Controller (EXDMAC)
(2)
When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three
cycles later. Once transfer is started, it continues (as a burst) until the transfer end condition is
satisfied.
If the BGUP bit is 1 in EDMDR, the bus is transferred in the event of a bus request from another
bus master.
Transfer requests for other channels are held pending until the end of transfer on the current
channel.
Figures 8.31 to 8.34 show operation timing examples for various conditions.
Rev. 1.00 Sep. 19, 2008 Page 442 of 1342
REJ09B0467-0100
φ pin
Bus cycle
CPU
operation
ETEND
EDA bit
Auto Request/Burst Mode/Normal Transfer Mode
CPU cycle CPU cycle
External
1
space
Figure 8.31 Auto Request/Burst Mode/Normal Transfer Mode
External
space
(CPU Cycles/Dual Address Mode/BGUP = 0)
EXDMA
External
space
read
EXDMA
write
EXDMA
read
EXDMA
write
Repeated
Last transfer cycle
EXDMA
read
EXDMA
write
CPU cycle
0