r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 454

• Manufacturer Part Number: r4f2456
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 8 EXDMA Controller (EXDMAC)
(5)
In block transfer mode, the specified number of transfers (equivalent to the block size) is
performed in response to a single transfer request. To ensure that the correct number of transfers is
carried out, a block-size transfer is always executed, except in the event of a reset, transition to
standby mode, or generation of an NMI interrupt.
If an NMI interrupt is generated during block transfer, operation is halted midway through a
block-size transfer and the EDA bit is cleared to 0, terminating the transfer operation. In this case
the BEF bit, which indicates the occurrence of an error during block transfer, is set to 1.
(6)
The IRF bit in EDMDR is set to 1 when an interrupt request source occurs. If the EDIE bit in
EDMDR is 1 at this time, an interrupt is requested.
The timing for setting the IRF bit to 1 is when the EDA bit in EDMDR is cleared to 0 and transfer
ends following the end of the DMA transfer bus cycle in which the source generating the interrupt
occurred.
If the EDA bit is set to 1 and transfer is resumed during interrupt handling, the IRF bit is
automatically cleared to 0 and the interrupt request is cleared.
For details on interrupts, see section 8.5, Interrupt Sources.
8.4.8
The priority order of the EXDMAC channels is: channel 2 > channel 3. Table 8.3 shows the
EXDMAC channel priority order.
Table 8.3
If transfer requests occur simultaneously for a number of channels, the highest-priority channel
according to the priority order in table 8.3 is selected for transfer.
Rev. 1.00 Sep. 19, 2008 Page 424 of 1342
REJ09B0467-0100
Channel
Channel 2
Channel 3
BEF Bit in EDMDR
IRF Bit in EDMDR
Channel Priority Order
EXDMAC Channel Priority Order
Priority
High
Low