r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 419

• Manufacturer Part Number: r4f2456
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

(5)
DREQ pin falling edge detection is performed in synchronization with DMAC internal operations.
The operation is as follows:
[1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and
[2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].
[3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and
After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer
is enabled is performed on detection of a low level.
(6)
At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge
sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request
is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that
occurs before write to DMABCRL to enable transfer.
switches to [2].
switches to [1].
Activation by Falling Edge on DREQ Pin
Activation Source Acceptance
Internal write signal
Internal read signal
External address
Figure 7.41 Example in which Low Level Is Not Output at TEND Pin
Internal address
HWR, LWR
TEND
φ
External write by CPU, etc.
Not output
DMA
read
Rev. 1.00 Sep. 19, 2008 Page 389 of 1342
Section 7 DMA Controller (DMAC)
DMA
write
REJ09B0467-0100