r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 1044

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r4f2456

Manufacturer Part Number
r4f2456
Description
16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

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Section 17 I
17.5
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK detection, STOP recognition, and arbitration lost. Table 17.3 shows the contents of each
interrupt request.
Table 17.3 Interrupt Requests
Interrupt exception handling is performed when the interrupt conditions listed in table 17.3 are set
to 1 and the CPU is ready to accept interrupts. During exception handling, the interrupt sources
should be cleared. Note, however, that TDRE and TEND are automatically cleared by writing
transmit data to ICDRT, and RDRF is automatically cleared by reading data from ICDRR. In
particular, if TDRE is set at the same time transmit data is written to ICDRT, and then TDRE is
cleared again, an extra byte of data may be transmitted.
Rev. 1.00 Sep. 19, 2008 Page 1014 of 1342
REJ09B0467-0100
Interrupt Request
Transmit Data Empty
Transmit End
Receive Data Full
STOP Recognition
NACK Detection
Arbitration Lost
Interrupt Request
2
C Bus Interface 2 (IIC2)
Abbreviation
TXI
TEI
RXI
NAKI
STPI
Interrupt Condition
(TDRE=1)
(TEND=1)
(RDRF=1)
(STOP=1)
{(NACKF=1)+(AL=1)}
(STIE=1)
(TIE=1)
(TEIE=1)
(RIE=1)
(NAKIE=1)

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