r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 1034

• Manufacturer Part Number: r4f2456
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 17 I
17.4.4
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal.
The transmission procedure and operations in slave transmit mode are described below.
1. Set the ICE bit in ICCRA to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
2. When the slave address matches in the first frame following detection of the start condition,
3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,
4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free.
5. Clear TDRE.
Rev. 1.00 Sep. 19, 2008 Page 1004 of 1342
REJ09B0467-0100
(master output)
(master output)
(slave output)
bits in ICCRA to 1. (Initial setting) Set the MST and TRS bits in ICCRA to select slave receive
mode, and wait until the slave address matches.
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS in ICCRA and TDRE in ICSR
are set to 1, and the mode changes to slave transmit mode automatically. The continuous
transmission is performed by clearing TDRE after writing transmit data to ICDRT every time
TDRE is set.
with TDRE = 1. When TEND is set, clear TEND.
User
processing
ICDRS
ICDRR
SCL
SDA
SDA
RCVD
RDRF
Slave Transmit Operation
2
C Bus Interface 2 (IIC2)
Data n-1
[5] Read ICDRR after setting RCVD.
A
Figure 17.8 Master Receive Mode Operation Timing 2
9
Data n-1
Bit 7
1
Bit 6
2
Bit 5
3
Bit 4
4
[6] Issue stop
Bit 3
condition
5
Bit 2
6
[7] Read ICDRR and clear RCVD
Bit 1
7
Bit 0
8
Data n
A/A
9
Data n
[8] Set slave
receive mode