r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 387

• Manufacturer Part Number: r4f2456
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

7.5.7
In block transfer mode, data transfer is performed with channels A and B used in combination.
Block transfer mode can be specified by setting the FAE bit in DMABCRH and the BLKE bit in
DMACRA to 1. In block transfer mode, a data transfer of the specified block size is carried out in
response to a single transfer request, and this is executed for the number of times specified in
ETCRB. The transfer source is specified by MARA, and the transfer destination by MARB. Either
the transfer source or the transfer destination can be selected as a block area (an area composed of
a number of bytes or words). Table 7.10 summarizes register functions in block transfer mode.
Table 7.10 Register Functions in Block Transfer Mode
MARA and MARB specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or
word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be
set separately for MARA and MARB. Whether a block is to be designated for MARA or for
MARB is specified by the BLKDIR bit in DMACRA.
To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N
transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL,
and N in ETCRB.
Figure 7.13 illustrates operation in block transfer mode when MARB is designated as a block area.
Register
23
23
15
Block Transfer Mode
7
7
ETCRAH
ETCRAL
ETCRB
MARA
MARB
0
0
0
0
0
Function
Source address
register
Destination
address register
Holds block
size
Block size
counter
Block transfer
counter
Initial Setting
Start address of
transfer source
Start address of
transfer destination
Block size
Block size
Number of block
transfers
Rev. 1.00 Sep. 19, 2008 Page 357 of 1342
Section 7 DMA Controller (DMAC)
Operation
Incremented/decremented
every transfer, or fixed
Incremented/decremented
every transfer, or fixed
Fixed
Decremented every
transfer; ETCRAH value
copied when count
reaches H'00
Decremented every block
transfer; transfer ends
when count reaches
H'0000
REJ09B0467-0100