r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 322

• Manufacturer Part Number: r4f2456
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 6 Bus Controller (BSC)
(a)
Rev. 1.00 Sep. 19, 2008 Page 292 of 1342
REJ09B0467-0100
Figure 6.91 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
DQMU, DQML
Precharge-sel
Address bus
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after continuous
synchronous DRAM space read access is disabled. Idle cycle insertion after continuous
synchronous DRAM space read access can be enabled by setting the DRMI bit to 1. The
conditions and number of states of the idle cycle to be inserted are in accordance with the
settings of bits ICIS1, ICIS0, and IDLC in RCR. Figure 6.91 shows an example of idle cycle
operation when the DRMI bit is set to 1. When the DRMI bit is cleared to 0, an idle cycle is
not inserted after continuous synchronous DRAM space read access even if bits ICIS1 and
ICIS0 are set to 1.
Normal space access after a continuous synchronous DRAM space read access
Data bus
CKE
CAS
RAS
WE
RD
Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2)
φ
PALL ACTV READ
Column
address
T
p
Continuous synchronous
DRAM space read
address
address
Row
Row
T
r
T
Column address 1
c1
T
cl
T
c2
Idle cycle
High
T
i
External space read
External address
External address
T
1
NOP
T
2
T
3
Continuous synchronous
DRAM space read
T
i
Column address 2
T
c1
READ
T
Cl
NOP
T
c2