r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 279

• Manufacturer Part Number: r4f2456
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

6.8.5
The synchronous clock (SDRAMφ) is output from the CS5 pin. SDRAMφ is shifted by 90° phase
from φ. Therefore, a stable margin is ensured for the synchronous DRAM that operates at the
rising edge of clocks. Figure 6.55 shows the relationship between φ and SDRAMφ.
6.8.6
The four states of the basic timing consist of one T
output cycle) state, and the T
When areas 2 to 5 are set for the continuous synchronous DRAM space, settings of the WAITE bit
of BCR, RAST, CAST, RCDM bits of DRAMCR, and the CBRM bit of REFCR are ignored.
Figure 6.56 shows the basic timing for synchronous DRAM.
Synchronous DRAM Clock
Basic Timing
SDRAMφ
Figure 6.55 Relationship between φ and SDRAMφ
φ
c1
and two T
c2
(column address output cycle) states.
T cyc
p
(precharge cycle) state, one T
Rev. 1.00 Sep. 19, 2008 Page 249 of 1342
1/4 T cyc (90°)
Section 6 Bus Controller (BSC)
r
REJ09B0467-0100
(row address