r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 459

no-image

r4f2456

Manufacturer Part Number
r4f2456
Description
16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
r4f24565NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
r4f24565NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
r4f24568NVFQV
Manufacturer:
REA
Quantity:
15
Part Number:
r4f24568NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
r4f24568NVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
r4f24568NVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
r4f24568NVZFQV
Manufacturer:
REA
Quantity:
5
Part Number:
r4f24568NVZFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
r4f24569DVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
r4f24569DVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
r4f24569VFQV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
(2)
Figure 8.16 shows an example of transfer when ETEND output is enabled, and word-size, normal
transfer mode (burst mode) is performed from external 16-bit, 2-state access space to external 16-
bit, 2-state access space.
In burst mode, one-byte or one-word transfers are executed continuously until transfer ends.
Once burst transfer starts, requests from other channels, even of higher priority, are held pending
until transfer ends.
If an NMI interrupt is generated while a channel designated for burst transfer is enabled for
transfer, the EDA bit is cleared and transfer is disabled. If a block transfer has already been
initiated within the EXDMAC, the bus is released on completion of the currently executing byte or
word transfer, and burst transfer is aborted. If the last transfer cycle in burst transfer has been
initiated within the EXDMAC, transfer is executed to the end even if the EDA bit is cleared.
φ
Address bus
RD
HWR
LWR
ETEND
Normal Transfer Mode (Burst Mode)
Figure 8.16 Example of Normal Transfer Mode (Burst Mode) Transfer
Bus
release
DMA read
DMA write DMA read DMA write DMA read DMA write
Burst transfer
Rev. 1.00 Sep. 19, 2008 Page 429 of 1342
Section 8 EXDMA Controller (EXDMAC)
Last transfer cycle
REJ09B0467-0100
Bus
release

Related parts for r4f2456