r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 374

• Manufacturer Part Number: r4f2456
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 7 DMA Controller (DMAC)
7.5.3
Idle mode can be specified by setting the RPE bit in DMACR and DTIE bit in DMABCRL to 1. In
idle mode, one byte or word is transferred in response to a single transfer request, and this is
executed the number of times specified in ETCR. One address is specified by MAR, and the other
by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6
summarizes register functions in idle mode.
Rev. 1.00 Sep. 19, 2008 Page 344 of 1342
REJ09B0467-0100
Idle Mode
Sequential mode setting
and transfer destination
Set number of transfers
Set transfer source
Read DMABCRL
Set DMABCRH
Sequential mode
Set DMABCRL
Set DMACR
addresses
Figure 7.4 Example of Sequential Mode Setting Procedure
[1]
[2]
[3]
[4]
[5]
[6]
[1] Set each bit in DMABCRH.
[2] Set the transfer source address and transfer
[3] Set the number of transfers in ETCR.
[4] Set each bit in DMACR.
[5] Read the DTE bit in DMABCRL as 0.
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
• Set the DTE bit to 1 to enable transfer.
• Clear the FAE bit to 0 to select short address
• Specify enabling or disabling of internal
destination address in MAR and IOAR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
• Clear the RPE bit to 0 to select sequential
• Specify the transfer direction with the DTDIR
• Select the activation source with bits DTF3 to
decremented with the DTID bit.
mode.
bit.
DTF0.
mode.
interrupt clearing with the DTA bit.
interrupts with the DTIE bit.